1. Field of the Invention
The present invention relates to a semiconductor device having capacitors and a manufacturing method thereof.
2. Description of the Prior Art
There is known a FeRAM (Ferroelectric Random Access Memory) having a ferroelectric as a non-volatile memory capable of storing information even if a power source is turned off. The FeRAM has a structure that it stores information by using the hysteresis characteristics of the ferroelectric, which can be operated in high-speed and has low power consumption, and its future development is expected as a non-volatile memory of frequent rewriting.
FIGS. 1A and 1B show circuit diagram examples of the memory cell of the FeRAM.
FIG. 1A shows the circuit diagram of a type where two transistors T11, T12 and two capacitors C11, C12 are used in storing 1-bit information (hereinafter, referred to as 2T2C type). In the 2T2C type FeRAM memory cell, a complementary operation is performed that data of “1” or “0” is stored in one capacitor and opposite data is stored in another capacitor, the polarization state of the both capacitors C11, C12 is read out in determining the data, and the data is determined based on the difference between the polarizations.
FIG. 1B shows the circuit diagram of a type where one transistor T0 and one capacitor C0 are used in storing 1-bit information (hereinafter, referred to as 1T1C type). In the 1T1C type FeRAM memory cell, either data “1” or “0” is stored in one capacitor C0, and has a reference capacitor C1 generating a reference voltage in order to determine whether the information written in the memory cell is the data “1” or “0”. One electrode that constitutes the reference capacitor C1 is connected to a bit line BIT. Data is determined based on a magnitude relation between the potential of the capacitor C0 and the potential of the reference capacitor C1.
When the memory cell of 1T1C type and the memory cell of 2T2C type are compared, a cell area of 1T1C type having less number of capacitors can be reduced.
An example of the structure of a conventional memory cell will be described as follows.
FIG. 2 shows a plan view of the 2T2C type memory cell, and FIG. 3 shows a sectional view at I—I line thereof. Note that an interlayer insulating film on a semiconductor substrate is omitted from illustration.
In FIGS. 2 and 3, a plurality of active regions (wells) 103 surrounded by an element isolation layer 102 are formed vertically and horizontally at an interval with each other on the surface layer of a semiconductor substrate 101. On each active region 103, two gate electrodes 105, which combine word lines WL extending in a Y-direction, are formed via a gate insulating film 104. The word lines WL are extended on the element isolation insulating film 102. In each active region 103, the first to the third impurity diffusion regions 107a, 107b, 107c are formed in the active regions 103 at both sides of the two gate electrodes 105.
One gate electrode 105 and the impurity diffusion regions 107a, 107b on its both sides constitute a MOS transistor T0, and another gate electrode 105 and the impurity diffusion regions 107b, 107c on its both sides constitute another MOS transistor T0. In other words, the two transistors T0 are formed on each active region 103. The transistors T0 and the element isolation insulating film 102 are covered with an insulative cover film 108, and the first interlayer insulating layer 109 is formed on the insulative cover film 108.
A plurality of capacitor lower electrodes 111 of a striped shape are formed on the first interlayer insulating film 109 and over the element isolation insulating film 109 in an X-direction at an interval, a plurality of ferroelectric films 112 having substantially the same shape as the electrode 111 are formed on the capacitor lower electrodes 111, and a plurality of capacitor upper electrodes 113 are formed on the ferroelectric films 112 in a line in the Y-direction. One capacitor upper electrode 113, the ferroelectric film 112 and the capacitor lower electrode 111, which are under the electrode 113, constitute a capacitor C.
Further, a second interlayer insulating film 114 is formed on the capacitor C and the first interlayer insulating film 109. Then, the first to the third contact holes 114a, 114b, 114c are formed in the first and second interlayer insulating films 109, 114 and the insulative cover film 108, which correspond to areas above the impurity diffusion regions 107a, 107b, 107c in the active region 103. The first to the third conductive plugs 115a, 115b, 115c are respectively formed in the first to third contact holes 114a, 114b, 114c. Furthermore, the fourth contact hole 114d is formed in the second interlayer insulating film 114, which corresponds to an area above the capacitor upper electrode 113, and the fourth conductive plug 115d is formed in the contact hole.
The first metal wiring 116a for connecting the first conductive plug 114a to the adjacent fourth conductive plug 115d is formed on the second interlayer insulating film 114. Further, the second metal wiring 116c for connecting the third conductive plug 114c to the adjacent fourth conductive plug 115d is formed on the second interlayer insulating film 114. Thus, a plurality of the capacitor upper electrodes 113 formed in a line over each capacitor lower electrode 111 are connected to the MOS transistor T0 one to one.
A metal pad 116b is formed on the second conductive plug 115b and on the second interlayer insulating film 114 around it. The metal pad 106b is connected to a bit line 117 that is to be formed over the pad via the third interlayer insulating film (not shown). The bit line 117 extends in a direction that intersects with each the word line WL and the capacitor lower electrode 111.
Incidentally, the 1T1C type memory cell also has a modified structure of the memory cell shown in FIGS. 2 and 3, and furthermore, a region where the reference capacitor is formed is required other than a memory cell region as shown in the following patent document 1.